rev. 1.2 - 3/31/98 1 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 pdm31564 description the pdm31564 is a high-performance cmos static ram organized as 262,144 x 16 bits. the pdm31564 features low power dissipation using chip enable (ce ) and has an output enable input (oe ) for fast memory access. byte access is supported by upper and lower byte controls. the pdm31564 operates from a single 3.3v power supply and all inputs and outputs are fully ttl- compatible. the pdm31564 is available in a 44-pin 400-mil plas- tic soj and a plastic tsop package for high-density surface assembly and is suitable for use in high- speed applications requiring high-speed storage. pdm31564 256k x 16 cmos 3.3v static ram a7-a0 memory
cell
array
256 x 128 x 32 row address
buffer control
logic sense amp column
decoder column
address
buffer row decoder clock
generator a15-a8 ce lb ub oe we data
input/
output
buffer vcc vss i/o15-i/o0 features n high-speed access times - com?: 8, 10, 12, 15, and 20 ns - ind: 12, 15, and 20 ns n low power operation (typical) - pdm31564sa active: 300 mw standby: 25mw n high-density 256k x 16 architecture n 3.3v ( 0.3v) power supply n fully static operation n ttl-compatible inputs and outputs n output buffer controls: oe n data byte controls: lb , ub n packages: plastic soj (400 mil) - so plastic tsop (ii) - t functional block diagram 512 x 256 x 32 a8 - a0 a17 - a9
pdm31564 2 rev. 1.2 - 3/31/98 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 15 16 29 30 31 32 a4
a3
a2
a1
a0
ce
i/o0
i/o1
i/o2
i/o3
vcc
vss
i/o4
i/o5
i/o6
i/o7
we
a17
a16
a15
a14
a13 a5
a6
a7
oe
ub
lb
i/o15
i/o14
i/o13
i/o12
vss
vcc
i/o11
i/o10
i/o9
i/o8
nc
a8
a9
a10
a11
a12
13 14 33 34 35 36 37 38 39 40 41 42 43 44 19 20
21
22 17 18 23 24 25 26 27 28
1 2 3 4 5 6 7 8 9 10 11 12 15 16 29 30 31 32 a4
a3
a2
a1
a0
ce
i/o0
i/o1
i/o2
i/o3
vcc
vss
i/o4
i/o5
i/o6
i/o7
we
a17
a16
a15
a14
a13 a5
a6
a7
oe
ub
lb
i/o15
i/o14
i/o13
i/o12
vss
vcc
i/o11
i/o10
i/o9
i/o8
nc
a8
a9
a10
a11
a12
13 14 33 34 35 36 37 38 39 40 41 42 43 44 19 20
21
22 17 18 23 24 25 26 27 28
pin con?uration soj capacitance (t a = +25 c, f = 1.0 mhz) note: this parameter is determined by device characterization, but is not production tested. symbol parameter conditions max. unit c in input capacitance v in = v ss 6pf c i/o output capacitance v i/o = v ss 8pf pin description name description a17-a0 address inputs i/o15-i/o0 data inputs ce chip enable input we write enable input oe output enable input lb , ub data byte control inputs nc no connect v ss ground v cc power (+3.3v) tsop (ii)
pdm31564 rev. 1.2 - 3/31/98 3 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 operating mode note: h = v ih , l = v il , x = don? care mode ce oe we lb ub i/o7-i/o0 i/o15-i/o8 power read l l h l l output output i cc h l high impedance output i cc l h output high impedance i cc write l x l l l input input i cc h l high impedance input i cc l h input high impedance i cc output disable l h h x x high impedance high impedance i cc l x x h h high impedance high impedance i cc standby h xxxx high impedance high impedance i sb absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect reliability. 2. appropriate thermal calculations should be performed in all cases and speci?ally for those where the chosen package has a large thermal resistance (e.g., tsop). the calculation should be of the form : t j = t a + p * q ja where t a is the ambient tempera- ture, p is average operating power and q ja the thermal resistance of the package. for this product, use the following q ja values: soj: 59 o c/w tsop: 87 o c/w recommended dc operating conditions symbol rating com l. ind. unit v term terminal voltage with respect to v ss ?.5 to +4.6 ?.5 to +4.6 v t bias temperature under bias ?5 to +125 ?5 to +135 c t stg storage temperature ?5 to +125 ?5 to +150 c p t power dissipation 1.5 1.5 w i out dc output current 50 50 ma t j maximum junction temperature (2) 125 145 c symbol description min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v v ss supply voltage 0 0 0 v industrial ambient temperature ?0 25 85 c commercial ambient temperature 0 25 70 c
pdm31564 4 rev. 1.2 - 3/31/98 preliminary power supply characteristics notes: all values are maximum guaranteed values. -8 -10 -12 -15 -20 symbol parameter com l com l com l ind. com l ind. com l ind. unit i cc operating current ce = v il 220 210 200 210 190 200 185 195 ma f = f max = 1/t rc v cc = max. i out = 0 ma i sb standby current ce = v ih 50 45 40 45 35 40 30 35 ma f = f max = 1/t rc v cc = max. i sb1 full standby current ce 3 v cc ?0.2v 10 10 10 15 10 15 10 15 ma f = 0 v cc = max., v in 3 v cc ?0.2v or 0.2v dc electrical characteristics (v cc = 3.3v 0.3v) note: 1. v il (min) = ?.0v for pulse width less than 20 ns. symbol parameter test conditions min. max. unit i li input leakage current v cc = max., v in = vss to v cc com?/ ind. ? 5 m a i lo output leakage current v cc = max., ce = v ih , v out = vss to v cc com?/ ind. ? 5 m a v il input low voltage ?.3 (1) 0.8 v v ih input high voltage 2.2 vcc + 0.3 v v ol output low voltage i ol = 8 ma, v cc = min. 0.4 v v oh output high voltage i oh = ? ma, v cc = min. 2.4 v
pdm31564 rev. 1.2 - 3/31/98 5 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 +3.3v 317 w 351 w d out 30 pf figure 1. output load figure 2. output load equivalent (for t lzce , t hzce , t lzwe , t hzwe, t lzbe , t hzbe , t lzoe , t hzoe ) +3.3v 317 w 351 w d out 5 pf ac test conditions input pulse levels v ss to 3.0v input rise and fall times 2.5 ns input timing reference levels 1.5v output reference levels 1.5v output load see figures 1 and 2
pdm31564 6 rev. 1.2 - 3/31/98 preliminary t aa t rc ub, lb oe ce addresses t oh t aoe t ba d out output data valid t lzbe (1) t lzoe (1) t lzce (1) t ace t hzce (1) t hzoe (1) t hzbe (1) read timing diagram ac electrical characteristics * v cc = 3.3v + 5% description -8* -10* ?2 ?5 ?0 read cycle symbol min max min max min max min max min max unit read cycle time t rc 8 10 12?5?0 ns address access time t aa 8 10?2?5?0ns chip enable access time t ace 8 10?2?5?0ns byte access time t ba 5 6???ns output hold from address change t oh 4? 4?? ns byte disable to output in low-z (1) t lzbe 0? 0?? ns byte enable to output in high-z (1) t hzbe 4 5???ns chip enable to output in low-z (1) t lzce 3? 4?? ns chip disable to output high-z (1, 2) t hzce 4 5???ns output enable access time t aoe 4 5?? 10ns output enable to output in low-z (1) t lzoe 0? 0?? ns output disable to output in high-z (1, 2) t hzoe 4 5???ns
pdm31564 rev. 1.2 - 3/31/98 7 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 write cycle 1 timing diagram (we controlled) t aw t as t wc ub, lb ce we addresses t wp t lzwe (1) t cw t bw high impedance t hzwe (1) t ah t dh t ds data stable (3) (4) d out d in write cycle 2 timing diagram (ce controlled) t aw t as t wc ub, lb ce we addresses t wp t cw high impedance t dh t ds data stable d out d in t ah t bw t lzbe (1) t lzce (1) t hzwe (1)
pdm31564 8 rev. 1.2 - 3/31/98 preliminary ac electrical characteristics * v cc = 3.3v + 5% description -8* -10* -12 -15 -20 write cycle sym min. max min. max min. max. min. max. min. max. unit write cycle time t wc 8 10?2?5?0 ns chip enable to end of write t cw 7? 10 11 13 ns address valid to end of write t aw 7? 10 11 13 ns byte pulse width t bw 7? 10 12 13 ns address setup time t as 0???? ns address hold from end of write t ah 0???? ns write pulse width t wp 7??? 10 ns data setup time t ds 5???? ns data hold time t dh 0???? ns byte disable to output in low z (1, 3, 4) t lzbe 0???? ns byte enable to output in high z (1, 3, 4) t hzbe ?????ns output disable to output in low z (1, 3, 4) t lzoe 0???? ns output enable to output in high z (1, 3, 4) t hzoe ?????ns write disable to output in low z (1,3, 4) t lzwe 0???? ns write enable to output in high z (1, 3, 4) t hzwe ? 6 ???ns write cycle 3 timing diagram (ub , lb controlled) t aw t as t wc ub, lb ce we addresses t wp t cw high impedance t dh t ds data stable d out d in t ah t bw t lzbe (1) t lzce (1) t hzwe (1)
pdm31564 rev. 1.2 - 3/31/98 9 preliminary 1 2 3 4 5 6 7 8 9 10 11 12 device type power speed package type process temp. range preferred shipping container commercial (0 to +70 c) industrial (?0 c to +85 c) 8 commercial only 10 commercial only 12 15 20 sa standard power blank i a automotive ( ?0 c to +105 c) blank tubes tr tape & reel ty tray pdm31564 - (256kx16) static ram xxxxx x xx x x x so 44-pin 400-mil plastic soj t 44-pin plastic tsop (ii) notes : 1. parameter is determined by device characterization and is not production tested. see figure 2 for load conditions. 2. if the ce low transition occurs coincident with or after the we low transition, outputs remain in a high imped- ance state. 3. if the ce high transition occurs coincident with or after the we high transition, outputs remain in a high imped- ance state. 4. if oe is high during a write cycle, the outputs are in a high-impedance state during this period. ordering information faster memories for a fasterworld
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